1. Field of the invention
The present invention relates in general to a semiconductor device such as semiconductor pressure sensor, semiconductor acceleration sensor or the like and a method of producing same. More specifically, the present invention is concerned with the semiconductor devices of a type and a method of producing same, which type comprises a silicon substrate, two mutually isolated electric parts arranged on the substrate, wiring or electrodes electrically connecting to or electrically connectable to the two electric parts, and means for connecting the wiring or the electrodes to an external electric device to keep the two electric parts at given potentials.
2. Description of the Prior Art
For producing a semiconductor device, there has been widely used a so-called "electrolytic etching method", which will be described in the following with reference to FIG. 7 which shows a semiconductor device SD-0.
In the drawing, denoted by numeral 1 is a P-type silicon substrate, and 3 is an N-type epitaxial layer formed on the silicon substrate 1. High density N-type diffused layers 4 are formed at given positions of the epitaxial layer 3. The diffused layers 4 are electrically connected through wiring layers 7. Denoted by numeral 5 is a high density P-type region (viz., isolating region) which is arranged to divide the epitaxial layer 3 into mutually isolated islands. Designated by numeral 6 is a wiring layer through which the potential of the silicon substrate 1 can be controlled. Designated by numerals 2a and 2b are oxide films covering the semiconductor device SD-0.
In order to produce the semiconductor device SD-0 from a silicon substrate, an electrolytic etching is carried out. For this etching, a solo called "stop etching method" is usually used, which uses the etching characteristic appearing in an interface between the P-layer and the N-layer. That is, in the method, etching of the silicon substrate is carried out in an alkaline etching liquid while applying, through the high density diffused layers 4, the epitaxial layer 3 with a positive voltage having a reference electrode immersed in the liquid. With this, suitable recesses are provided in the silicon substrate.
However, the above-mentioned method has the following drawback. That is, if, due to failure in photo-printing, the silicon substrate has a part through which a P-type region and an N-type region are electrically connected, a certain leakage current is forced to flow from the N-type region to the P-type region at the time of electrolytic etching. This causes a certain potential drop of the epitaxial layer 3, resulting in that the etching fails to stop at the interface defined between the P-layer and the N-layer. Of course, in this case, desired recesses are not provided in the semiconductor device SD-0.
One method for solving the above-mentioned drawback is shown in Japanese Patent First Provisional Publication 3-209778. In this method, the leakage current is detected by applying a junction (viz., PN-junction) of the P-layer and the N-layer with a reverse voltage, and the electrolytic etching is actually made to the silicon substrate only when the detected leakage current is smaller than a predetermined value.
However, due to its nature, the method of the publication fails to obtain a desired yield of products. That is, in this method, when the detected leakage current is greater than the predetermined value, etching is not made to the silicon substrate. In fact, this silicon substrate can not be used any longer, resulting in a poor yield of the products.